Common-drain circuit

A common-drain circuit is shown in Fig. 1. This circuit has the collector at signal ground. It is sometimes called a source follower. The FET is biased in the same way as for the common-source and common-gate circuits. In the illustration, an N-channel JFET is shown, but any other kind of FET could be used, reversing the polarity for P-channel devices. Enhancement-mode MOSFETs would need a resistor between the gate and the positive supply terminal (or the negative terminal if the MOSFET is P-channel).
The input signal passes through C2 to the gate. Resistors R1 and R2 provide gate bias. Resistor R3 limits the current. Capacitor C3 keeps the drain at signal ground. Fluctuating dc (the channel current) flows through R1 as a result of the input signal; this

Fig. 1: Common-drain circuit configuration.

causes a fluctuating dc voltage to appear across the resistor. The output is taken from the source, and its ac component passes through C1.
The output of the common-drain circuit is in phase with the input. This scheme is the FET analog of the bipolar common-collector arrangement. The output impedance is rather low, making this circuit a good choice for broadband impedance matching.